On-Chip Relative Single-Event Transient/Single- Event Upset Susceptibility Test Circuit for Integrated Circuits Working in Real Time

With technology scaling down, scale of the integrated circuit (IC) increases rapidly. It is unrealistic to harden every element in the IC, hence it is critical to evaluate relative single-event transient (SET) or single-event upset (SEU) sensitivity of each node in the IC to selectively harden the elements connected to the identified highly sensitive nodes. Therefore, this paper proposes a test circuit to measure the relative SET/SEU sensitivity of each node in any circuit working in real time. This will have significant implications for designing ICs with high reliability and low overheads.