Design and implementation in FPGA of a CIC interpolation filter for software defined radio

The vision of a software defined radio (SDR) is to implement in different software systems of communications using the same hardware platform. An advanced SDR system consists of two fundamental components: a programmable RF component and another reconfigurable FPGA-based component in charge of performing high-speed signal processing. Since the sampling rate of the ADC and DAC converters is generally fixed and well above the rates required for the baseband processing of different communications systems, the SDRs employ programmable modules that perform the real-time processing rate changes. This article describes in detail the design and implementation in FPGA of a programmable CIC interpolator filter. By selecting the number of steps, the rate change and the delay factor, the frequency rejection is also configured, which could generate intermodulation problems in the RF step. It also describes the validation test and the analysis of resources used in FPGA.