Effect of cheese and fill procedures on the manufacturability and yield of RF integrated circuits

With the emerging trends in RF design domain, semiconductor process technology has also evolved to meet the stringent design requirements. Owing to better electromigration resistance, low resistance and dielectric constant, scalability, ability to handle higher current densities and efficient power consumption, copper interconnects have emerged as the widely accepted metallization option to aid silicon performance improvements. At the same time, due to thickness variations and continuous shrinkage of interconnect feature sizes, chemical mechanical polishing (CMP) processes have become challenging. This paper covers the intricacies of the CMP processes and methodologies to overcome the process difficulties encountered with copper interconnects. The need for damascene and dual damascene processes have been emphasized. Cheese and fill procedures are of prime importance to aid better manufacturability and higher yield. This paper talks about the cheese and fill procedures adopted by foundries and the extent of care taken so that the expected circuit performance doesn't get affected in any way. The importance of copper interconnects and the key contribution of the cheese and fill procedures in the successful implementation of silicon realization for RF product designs have been discussed.