Analysis of GDI logic for minimum energy optimal supply voltage

As technology advances towards the deep sub-micron regime, energy consumption of digital circuits is becoming more serious. Supply voltage (V
DD
) scaling is the effective knob to achieve minimum energy consumption. This paper aims at obtaining the minimum energy optimal V
DD
for the design of Gate Diffusion Input (GDI) logic circuits. A 10 transistor (10T) GDI based full adder circuit is designed for analyzing the performance of GDI logic to obtain optimal V
DD
. Extensive simulations were performed using different supply voltages ranging from 100mV to 1V using the cadence 45nm CMOS process technology. The simulations have shown that the operation of GDI based design at optimal V
DD
of 0.4V, lead to energy savings of more than 69% in comparison with the strong inversion counterparts. The expressions for energy using GDI logic have also been presented.