Application of full chip OPC to quarter micron logic device

Model based full chip Optical Proximity Correction (OPC) was applied to logic devices with a minimum gate length of 0.24 /spl mu/m. Two empirical models were used in order to correct for both the 1D optical proximity effect and the 2D optical proximity effect simultaneously. OPC features such as line bias and hammer head were effective in reducing critical dimension variation and line shortening. Increased process margin and reduction in interconnection resistance were obtained.