A cobalt salicide CMOS process with TiN-strapped polysilicon gates

A submicrometer CMOS technology with MOSFET structures consisting of a TiN-strapped polysilicon gate electrode and self-aligned cobalt silicided source/drain junctions is developed. It is shown that the TiN-strapped gates provide a low-sheet-resistance gate electrode without threshold voltage instabilities caused by the lateral dopant interdiffusion of silicided gates. Cobalt silicide creep over the sidewall spacer, which can result in bridging between the source/drain and gate, is also eliminated. Since the source-drain regions are silicided with CoSi/sub 2/, shallow, low-leakage junctions are obtained.<
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