SOI MOSFET fluctuation limits on gigascale integration (GSI)

Intrinsic and extrinsic threshold voltage (V/sub ts/) fluctuations in fully depleted (FD) single gate (SG) and dual gate (DG) SOI MOSFETs as well as partially depleted (PD) SOI MOSFETs are investigated using novel 3D compact physical models. Threshold voltage maximum deviations due to intrinsic random dopant placement can escalate to more than /spl plusmn/100% for sub-100 nm technology generations. Much smaller (<1.5 mV) intrinsic threshold voltage fluctuations in undoped SOI MOSFETs are explored.