Selected aspects and tradeoffs in transistor level implementation of genetic algorithms

In this paper we focus on the issues of hardware implementation of genetic algorithms (GA) in hardware. In their classic implementation, the genetic algorithms search for a global minimum or maximum of a multidimensional function called the fitness function. If the problem, i.e. the fitness function, is too complex for a brute force search, we can look for a solution based on GA. In this situation we obtain desired results by performing parallel calculations on the “generation” of candidate solutions randomly distributed over the input data space. For these candidates we evaluate the fitness function and then we breed a next generation. During breeding we use operators that mimic chromosomal crossing to exchange of features between the candidates, and mutation operations to introduce new features into the population. The literature research shows that more than sixty different crossing algorithms are used with the GA in different purposes. Such a large number of crossing algorithms is a serious problem when developing a hardware solution. In this paper, we are reviewing a deployment of selected crossing operators in specialized hardware.