Double-regenerated switched-current comparator

A double-regeneration (DR) technique in switched-current comparators is described in this paper. The technique uses the comparator's memory transistors not only as a calibration stage but also as a regenerative amplifier. This provides an enhanced speed with no penalty on noise and minimum added complexity and power. Practical simulation indicates a multiplexed DR comparator operating at a promising bandwidth of 270 MHz which is an improvement in speed by a factor of /spl sim/1.35 over the multiplexed basic comparator.