An efficient VLSI implementation of four-step search algorithm

Four-step search (4SS) performs better than the well known three-step search (3SS) and the new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation focuses on power reduction through a power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40%.