On-chip-variation-aware power-mode-aware buffer synthesis for clock skew minimization

Multi-power-mode designs have been widely used in industry for reducing the power consumption. However, in an ultra-low voltage design, a huge clock skew may occur among different power modes. The previous work has proposed a two-stage approach to eliminate this huge clock skew, but they do not consider the skew caused by the on-chip-variation (OCV) effects. In this paper, we propose an approach to deal with this problem. The proposed approach has the following two features. First, we adopt the dynamic self-adjusting mechanism during the circuit execution. Second, we take both the OCV-induced skew and the self-adjusting mechanism into account during the power-mode-aware buffer (PMAB) synthesis. Benchmark data consistently show that our approach achieves good results.