High speed low power true single phase clock CMOS divide by 2/3 prescaler

A new true-single-phase-clock (TSPC) divide-by-2/3 prescaler is presented in this work. By merging one of the branches of the TSPC D flip-flops (DFF) and the modified dual-modulus control circuit, we can realize a divide-by-2/3 prescaler with only 5-stage TSPC logic gates and fewer transistors compared with the conventional designs. Analysis shows that the load capacitance at output of the proposed prescaler can be much reduced, and the prescaler can operate as fast as a single TSPC flip-flop when working in the divide-by-3 mode. The proposed prescaler and the recently published works are both simulated in a low power 65nm CMOS process. From the simulation results, it is shown that the proposed divide-by-2/3 prescaler demonstrates the highest power efficiency among the referenced designs.