A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation

Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynamic voltage and frequency scaling technique is used to reduce the power consumption while different error recovery techniques are used to tolerate the process, voltage, and temperature variations. These techniques reduce the throughput by scaling down the frequency or flushing and restarting the errant pipeline. A resilient microarchitecture is introduced in this paper to tolerate the induced delays generated by the voltage scaling and the process, voltage, and temperature variations. This resilient microarchitecture detects and recovers the induced errors without flushing the pipeline and without scaling down the operating frequency. A resilient 16 b × 16 b MAC unit was fabricated using Global Foundry 65-nm technology with 18.26% area overhead and upto 1.65× speedup. At the typical conditions, the maximum frequency of the conventional MAC unit is about 375 MHz while the resilient MAC unit operates correctly at a frequency upto 620 MHz. In case of variations, the resilient MAC unit tolerates induced delays up to 50% of the clock period while keeping its throughput equal to the conventional MAC unit's maximum throughput. At 375 MHz, the resilient MAC unit is able to scale down the supply voltage from 1.2 to 1 V saving about 29% of the power consumed by the conventional MAC unit.