RTL design of a dynamically reconfigurable cell array for multimedia processing

This paper presents the design of a Coarse-grained Reconfigurable Architecture (CGRA), called MUSRA (Multimedia Specific Reconfigurable Architecture). The MUSRA is proposed to exploit multi-level parallelism of the computation-intensive loops in multimedia processing applications. To solve the huge bandwidth requirement of parallel processing arrays, the proposed architecture focuses on the exploitation of data locality to reduce data access bandwidth and increase efficiency of pipelined execution of the kernel loops. The MUSRA also supports the capability of dynamic reconfiguration by enabling the hardware fabrics to be reconfigured into different functions even if the system is working. The proposed architecture has been modeled at Register Transfer Level (RTL) by using VHDL language. Some benchmark applications have been mapped onto the MUSRA in order to validate the high flexibility and performance of the architecture that is suitable for a wide range of multimedia processing applications. The proposed CGRA can be applied as a reconfigurable hardware IP (Intellectual Property) core in reconfigurable high-performance System-on-Chips.