Approximate adder segmentation technique and significance-driven error correction

Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead of strict accurate computation, relaxed requirements might increase performance and reduce power consumption with a simplified or inaccurate circuit. One of the recent remarkable research efforts is the accuracy-configurable approximate adder designs, which can gracefully operate in both approximate (inaccurate) and accurate modes. In this paper, a novel technique for segmenting approximate adders was proposed by adding new bit locations that exploit the carry kill signal definition to limit carry propagation at specific locations. Moreover, a light-weight carry-in prediction and error detection techniques were proposed. For error recovery circuit, a significance-driven configurable correction stages were implemented, which imply a fast convergence to exact outputs with a very low magnitude of errors. The proposed design showed improvements of (16%) and (18.6%) for dynamic power and area respectively. Nevertheless, outputs reserved a general high accuracy level, which limited between 99% and 100% for the majority of input space. The proposed design was implemented in an image filter application, which resulted in high PSNR values of (53 and 83 db) for the two premier correction stages, and 100% exact results for the highest accuracy mode.