A 16–20 GHz LO system with 115 fs jitter for 24–30 GHz 5G in 28 nm FD-SOI CMOS

A system for mmW LO signal generation targeting 5G is presented. The proposed concept achieves high LO spectral purity at mmW frequencies using standard CMOS SOI technology. The measured performance is in line with 5G outdoor system requirements, which due to multi-path propagation require a smaller sub-carrier spacing than recent indoor mmW systems like IEEE 802.11ad. A set of two fractional-N, PLL based frequency synthesizer instances of the scalable LO system proposed has been implemented in 28 nm FD-SOI CMOS technology, where the chip area of one instance is only 0.11 mm
²
. Each PLL achieves an in-band phase noise below -100 dBc/Hz for a 28 GHz carrier while consuming just 15 mW from a 1.2 V supply. The FoM
_j
is -244 dB which is the best reported figure for a fractional-N PLL in this frequency range.