A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS

This paper presents a 60 GHz class-E digital power amplifier (DPA) that generates energy-efficient, non-constant envelope modulations up to 25 Gb/s. The DPA achieves a peak drain efficiency of 17.7% at a V
_sat
of 7.4 dBm. By means of direct digital amplitude modulation of the 6-bit output stage, the DPA produces error-free, high-order constellations (16-QAM, 32-QAM, 64-QAM) up to 5 GSym/s with error vector magnitudes (EVMs) <;-26 dB. Compared to prior 60 GHz DPAs, >3.5X higher data rates at comparable average efficiencies is achieved.