A 0.11mm2 164dB-FOM 0.18μm CMOS pipelined ADC with novel passive amplification

A 25MS/s 70.1dB-SNDR 5.3mW 0.11mm
²
pipelined ADC has been achieved by the low-cost 0.18μm CMOS. The proposed simple MDAC is implemented by only capacitors, switches, power supply voltage and source-follower buffer without requiring the dedicated voltage reference to attain the passive residue amplification. The prototype has achieved by far the smallest chip size and the excellent Schreier FOM of 164dB among 0.18μm CMOS pipelined ADCs without using low-V
_T
MOS and aggressive MDAC scaling.