Instruction fetch mechanisms for multipath execution processors

Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penalties incurred by branches that are difficult to predict. This paper presents efficient instruction fetch architecture designs for these multipath processor execution cores. We evaluate a number of design trade-offs for the first-level instruction cache and the multipath PC fetch arbiter. Furthermore we evaluate the effect of additional bandwidth limitations imposed by the processor frontend pipeline. Our results show that instruction fetch support for efficient multipath execution can be achieved with realizable hardware implementations. In addition, we show that the best performing instruction fetch designs for multipath execution and multithreaded processors are likely to differ, since both designs optimize the processor for different performance goals (minimal execution time vs maximal throughput).