Segmented spline hardware design for high dynamic range video pre-processor

Digital video capturing generates a huge amount of data to be processed and stored, which requires the use of compression techniques. Efficient hardware designs for real-time encoding are mandatory, especially for embedded systems, due to their performance and energy constraints. High Dynamic Range (HDR) video is a new technology that tends to be present in the next generation of devices in order to improve the video quality. However, the particularities of this kind of video incur in increased data to be stored and require support for special features in video processors/codecs. The current approach includes a pre-processor annex to an encoder to convert the HDR videos to a format that can be handled. This work presents a hardware design for the most time-consuming process within the HDR pre-processor, the Segmented Spline. The hardware design was developed based on hardware-oriented mathematical simplifications of the Segmented Spline, which reduce about 50% the number of basic operators. The developed architecture was synthesized for an Altera Stratix V FPGA, and the synthesis results show the optimized hardware can work at 17.56MHz using approximately 11k ALMs.