Sleep convention logic isochronic fork: An analysis

Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. Furthermore, due to their inherent robustness, such circuits are also promising for deep voltage scaling applications, where delays are orders of magnitude larger. However, QDI design has an Achilles heel, which is its associated area and power overhead penalties. These can hamper the adoption of this kind of design in current and future technologies. A recently proposed asynchronous circuit design template, the Sleep Convention Logic (SCL), does reduce these overheads significantly. SCL is an enhancement of the Null Convention Logic, a well-known asynchronous circuit QDI design template. This paper analyzes the architecture of circuits based on SCL, identifies and models associated timing constraints that were not described before. The paper also shows experimentally that respecting such constraints is fundamental to guarantee correct operation of these circuits, especially under low voltage supplies.