Yield impact of cross-field and cross-wafer CD spatial uniformity: collapse of the deep-UV and 193 nm lithographic focus window

The 0.13 /spl mu/m semiconductor manufacturing generation, shipping as early as 2001, will have transistor gate structures as small as 100 nm, creating a demand for sub-10 nm gate linewidth control. Linewidth variation consists of cross-chip, cross-wafer, cross-lot, and run-to-run components. In this work, we explore spatial dependencies across the lithographic field due to reticle error and across the wafer due to wafer and chuck nanotopography. Both sources of spatial variation can cause collapse of the lithographic focus window near the limits of resolution, resulting in CD excursions for gate structures in high-performance microprocessors. Our work supports the contention that photolithography-induced defects may become the primary source of yield loss for the 0.13 /spl mu/m generation and beyond.