Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations

In semiconductor wafer fabrication time constraints between process steps in furnace and wet etch causes a lot of problems for shop floor control to achieve cycle time targets and maximize machine utilization. Infineon Technologies Dresden has conducted a study, using discrete event simulation, to investigate the actual situation in the factory and to identify recommendations, to eliminate or to reduce the impact of time constraints. This paper presents a 2-day reduction in total cycle time, after implementation of findings in the factory.