Stacked nanowires/nanosheets GAA MOSFET from technology to design enablement

GAA nanowires (NW) transistors are promising candidates for sub 10 nm technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. Horizontally stacked they are a natural extension of today's mainstream technology. Considering enlarged NWs in Nanosheets (NS) allows to target the best compromise in power and performance for future applications. In this paper we will first briefly introduce the technology and then review what can bring advanced simulation focusing on both mobility and contact resistance. Then we will focus on devoted compact modeling fed by both TCAD capturing electrostatics of the Device and above mentioned advanced simulation for mobility. Finally we will demonstrate the capability of the model to capture actual hardware data as well as to benchmark the different architectures in competition down to 5 nm technology node.