Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA

According to the wide developments in the area of communications, there is a demand for secure system for data transmissions. In this paper, a Hash system SHA-1 and SHA-2 Processor is designed using Xilinx Spartan-3AN. The implementation of the processor is done by using Multithreading MIPS (Microprocessor without Interlocked Pipelines) single cycle by choosing a certain number of instructions that was necessary to invoke the SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 algorithm.