Design of area and power efficient full adder in 180nm

This paper presents a high drivability of full adder with less area and power consumption. This GDI based full adder is implemented by using both gate diffusion input (GDI) technique and pass transistor logic that leads to be a reduced area and power. To reducing the static power, ultralow power diode (ULPD) is used. The leakage current of this diode lies within the range of pA. The comparison has been done between existing systems like CMOS, CPL and hybrid full adders with proposed full adder. All full adders are designed with gpdk 0.18 um in Cadence Virtuoso schematic, and simulations are done in a Spectre Simulator.