Implementation and verification of MASH 1-1-1 for fractional-N frequency synthesizer in Zynq-7000 series SoC platform

The Delta-Sigma Modulator (DSM) is predominantly used to control the fractional division part of the PLL based Fractional-N Frequency Synthesizer. In this paper a third order Multi Stage Noise Shaping (MASH) Delta-Sigma Modulator architecture is designed using Verilog code. Simulated output is implemented in a SoC based Field programmable gate array (FPGA), Zynq 7000 series and output is verified using DSO.