UDGMOSFET based analog circuit blocks in cadence virtuoso

In the present study, a look up table (LUT) based approach is used to extract device characteristics of an SOI based UDGMOSFET built in TCAD and imported to Cadence Virtuoso to implement analog circuit blocks. In particular, this study utilizes the custom 14nm UDGMOSFET to build a simple CMOS inverter, a single ended voltage amplifier and a Schmitt Trigger circuit. The circuits are simulated in Cadence Virtuoso environment and the performance is compared with results obtained from similar simulations in TCAD, the motivation being to prove that analyses can be conducted in Cadence with comparable efficiency as TCAD but in significantly shorter duration of time.