High-efficiency cascade based design of doherty amplifier for wireless applications

In this paper a CMOS Doherty Power Amplifier operating at 2 GHz frequency is presented. The Doherty power amplifier (DPA) maximizes the power amplifier efficiency and simultaneously maintains amplifier linearity for signals having high Peak to Average Power Ratios (pAPR). The proposed design is simulated in 180nm CMOS technology. The design consists of two sub-power amplifiers, a 3dB Coupler, and a combining network. The combining network is implemented using impedance inverter which is realized using microstrip line. This design effectively amplifies the signals over the frequency range 1.8GHz to 2.4GHz.