Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates in 90nm Technology

The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. A 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 90 nm technology. The results from the proposed system are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 52.2 % for three transistor XNOR gate and 42.11 % for eight transistor full adder. It is also observed that the delay is reduced by 28.5 % for three transistors XNOR gate and 22.3 % for eight transistors full adder.