Two-way circuit partitioning by iterative improvement and logic perturbation

In this paper, we present five algorithms that simultaneously consider both the graph domain and logic domain for two-way min-cut circuit partitioning, To handle both domains, the iterative improvement and logic perturbation techniques are employed. The experimental results show that our algorithms are capable of generating better or comparable partitioning results as compared to the algorithm presented by Cheng et al. (1995).