Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations

Process variations have become a major challenge with the advancement in CMOS technologies. The performance of memory sub-systems such as Static Random Access Memory (SRAMs) is heavily dependent on these variations. Also, the VLSI industry requires the SRAM bit cell to qualify in the order of less than 0.1ppb to achieve higher Yield (Y). This paper proposes an efficient qualitative statistical analysis and Yield estimation method of SRAM sub-system which considers deviations due to variations in process parameters in bit line differential and input offset of sense amplifier (SA) all together. The Yield of SRAM is predicted for different capacities of SRAM array by developing a statistical model of memory sub-system in 65nm bulk CMOS technology. For the sub-system with 64 bit cells, it is estimated that the probability of failure is 4.802 * 10
^-13
in a read cycle of frequency 1GHz. Furthermore, the probability of failure for 8MB capacity is 5.035 * 10
^-7
while for 2GB capacity it increases to 1.289 * 10
^-5
. It is also observed that as the load on one SA per column is doubled, the probability of failure of memory slice increases by 70%. The proposed technique estimates the Yield(Y) for SRAM array to be more than 99.9999.