Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V
_BD
) and low holding voltage (V
_h
) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.