The segmented SCRs with optimized holding voltage for on-chip ESD protection

Segmentation technique for optimizing the holding voltage of SCR is discussed and implemented in a 0.6μm SOI process. Based on the prior researches, the holding voltage of SCR is a key parameter for latch-up risk assessment. The segmented SCR with external resistor paralleled with the parasitic Ptub resistor is proposed by modifying the layout, and the holding voltage can be increased. The TLP characterization results show that the holding voltage is affected by the ratio, width of the segmentations and the resistance of the external resistor. The factors related to the holding voltage can be traded off for specific applications. Meanwhile, the equivalent schematics and mechanism of the proposed structures are also investigated briefly in this paper.