Logic circuit failure analysis & micro-probing on floating signal net

With process technology development and circuit density rapidly increases, shrinkage of semiconductor device geometries has become extremely difficult to effectively analyze defect. Therefore, an exactness failure analysis process flow and technique need to be considered in order to analyze the failure mechanism, especially complex failure analysis such as failure of open/floating signal net in logic circuit. This paper outlines the electrical fault localization process flow, idea of layout/circuit study and electrical micro-probing measurement for net signal tracing. Subsequently, a floating signal net is isolated by passive voltage contrast (PVC) localization analysis. Upon fault localization, a complete physical analysis through focused ion beam (FIB) is most appropriate method for defect identification.