Electrical characterization of gate electrode recess depth in ultra-thick SiO2, vertical trench DMOS

In this paper, we present the experimental I-V and C-V characterization of vertical trench DMOS with different gate electrode recess depths. NBTI/PBTI test, via static bias stress test method was also performed in order to identify possible contaminations of the channel region. Effects of increasing this recess depth on the main electrical and capacitance performances are accurately measured. We concluded that the gate electrode resistance increases by +0.8ohm.cm−2/nm, gate-source charge reduces by −3.2pC/nm, blocking capability reduces by −7.4mV/nm and threshold voltage reduces by −1.3mV/nm respectively. However, NBTI/PBTI test showed that too deep gate electrode recess leads to thinning of protective oxide during source implant, causing Phosphorus dopant to cross-contaminate the channel region. For 300nm < < 650nm, NBTI/PBTI test needs to be performed to check for contamination but for d
recess
>650nm, contamination was clearly detected.