Simple die-level backside thinning sample preparation method for failure localization

In this paper, we present one simple die-level backside silicon thinning preparation approach to enable fault localization of vertical trench or highly doped silicon substrate power semiconductor devices. The methodologies are illustrated for understanding and immediate application at any lab environment. Effectiveness of the method is evaluated through qualitative judgement of image resolution clarity. Images characteristic are obtained from scanning optical microscopy (SOM) imaging techniques which is widely used for silicon backside analysis.