Highly efficient and linear class-E CMOS digital power amplifier using a compensated Marchand balun and circuit-level linearization achieving 67% peak DE and −40dBc ACLR without DPD

A highly efficient and linear wideband digital polar CMOS class-E power amplifier (DPA) is presented. Using a compensated wideband Marchand balun with re-entrant coupled lines for the output matching network, more than 50% peak drain efficiency over 2.2-3GHz with 16-17dBm Pout are achieved. The linearity is significantly improved by nonlinearly sizing the DPA array along with overdrive-voltage control and concurrent multiphase RF clocking. The chip prototype is fabricated in 40nm bulk CMOS and the balun is fabricated on a two-layer PCB. Measured results show -40dBc for a 40MHz QAM signal at 2.6GHz without using any sort of DPD. The measured peak Pout, DE and PAE at 2.6GHz are 17.2dBm, 67% and 45% with VDD=0.7V.