A 950MHz RF 20MHz bandwidth direct RF sampling bit streamer receiver based on an FPGA

A 950 MHz direct RF sampling bit streamer receiver architecture based on a Field Programmable Gate Array (FPGA) is presented. In proposed architecture, an RF input signal is divided into the envelope and phase detectors. They are directly converted to two 1 bit streams using multi-gigabit transceivers on an FPGA, then are reconstructed into I/Q signal in an FPGA. The measured error vector magnitudes are 2.7 % and 8.4 % for QPSK 5 MHz and 64-QAM 20 MHz input signals respectively. The architecture provides major benefits of eliminating ADC devices, simplifying the inter-connection of RF front end devices to digital base band, and cutting down the power consumption significantly for the multi-channel RF systems.