Using Verilog simulation libraries for ATPG

Significant engineering effort is invested into coding libraries for automatic test pattern generation (ATPG) and verifying their equivalence with corresponding "golden" simulation libraries. These tasks are greatly simplified by using the methodology and the ATPG described in this paper. Simulation libraries are read-in with little or no recoding. Various structural and some behavioral Verilog constructs are automatically converted into efficient gate-level models for ATPG.