A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data

Monolithic ICs are growing so large that tester capacity is rapidly becoming a problem. There are also a number of "stored pattern" test methods which vie for limited tester resources. From a quality perspective, how do we best allocate tester memory or time? In this paper, the SEMATECH Test Methods data are used to examine this important question.