A novel time expansion method to cope with simulator delay in the hardware-in-the-loop study of hysteresis current control

In recent years, Hardware-In-the-Loop (HIL) simulation such as RT-LAB, RTDS are widely used in power electronic system study. In order to keep the simulation accuracy, the main concern of researchers normally focuses on the minimum simulation step size of the simulator, while neglects the role of input-to-output delay of the simulator. Concentrating on the study of hysteresis current control of grid connected converter, this paper investigates the importance of the simulator delay. With theoretical analysis, simulation and experiments, it is found out that the delay of the simulator seriously affects the control performance: it can apparently increase the hysteresis current band, reduce the switching frequency, increase the current THD (Total Harmonic Distortion) and therefore deteriorate the control. With the input-out-delay, even if the simulation step is kept small, the simulation results are neither accurate nor trustable. Upgrading the simulator hardware to reduce the delay might be feasible in future but definitely very costly. While upgrading hardware is not a final solution, as an alternative software solution, this paper proposes a novel time expansion method. The experimental results prove that the proposed time expansion method can effectively cope with simulator delay in the HIL study of hysteresis current control, making it possible to achieve satisfactory performance with an ordinary simulator.