Power and area optimization of decimation filter for application in Sigma Delta ADC

The decimation filters find application in Sigma-Delta ADCs to decimate its oversampled output data to Nyquist sampling rate. The decimation filters determine the overall performance of the ADC as it occupies most of the area and power consumption. Therefore, this paper proposes the decimation filter design using the Cascaded Integrated Comb (CIC) filter to optimize the performance of XV ADC with respect to its area and power consumption. The design consists of a three stage decimator i.e. two FIR filters and a CIC filter. The design for the decimation filter is initially simulated in SIMULINK to verify its functionality and later the Simulink blocks are replaced by DSP blocksets in Xilinx System generator and the design is co-simulated on Zynq XC7Z020 FPGA board using Xilinx ISE software in Verilog language. The proposed design has a power consumption of 9mW and uses 2131 number of logic elements and has an 82.95% improvement in the number of slice registers used.