Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain

The Static Random Access Memory (SRAM) directly impacts the performance of the modern multi-core processor. Hence, the power, performance and area metrics are very crucial for SRAM design. In this article, we have successfully designed 10 nm TFET based 6T SRAM circuit at reduced supply voltage of 0.5 V. We also have optimized the circuit for high density, high performance, intermediate (trade-off between high density, high performance) 6T SRAM application. Later, we have estimated the dynamic “Read” power, “Read” energy, “Write” power, “Write” energy. The performance metrics: “Read” delay and “Write delay” are also analyzed precisely. These power, energy, delay metrics are also compared against the existing 10nm FinFET.