An FPGA-based algorithm development framework for estimating the accuracy of embedded DSP signal transforms

This work addresses the problem of estimating the accuracy of a certain class of digital signal processing algorithms, known as linear signal transforms, when implemented on field programmable gate array (FPGA) hardware computational structure (HCS) units. A solution is provided through the formulation of a hardware development framework which uses complex multipliers and complex addition units as its basic functional primitives to arrive at an estimation formulation of embedded signal processing operations.