A 2.8–3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS

We present a digital phase-locked loop (DPLL) operating from 2.8 to 3.8 GHz with an on-chip 40-MHz reference crystal oscillator. The DPLL makes use of a class-D digitally controlled oscillator and a digital-to-time converter with a single-bit (bang-bang) phase detector. The DPLL displays an excellent behavior in terms of in-band fractional spurs, which are consistently below -65 dBc across the tuning range, thanks to a number of digital correction algorithms running in the background. The 65-nm CMOS DPLL consumes 18.2 mW for an in-band phase noise of -102 dBc/Hz at 100-kHz offset.