CMOS mixed signal SoC for low-side current sensing

A switched capacitor low-side current sensing signal conditioning circuit with high dynamic range is demonstrated in AMS 0.35 μm, 3.3 V CMOS process. The design incorporates a Switched Capacitor Programmable Gain Amplifier (SC-PGA) and multi-bit second order ΔΣ-ADC. The switched capacitor eliminates the need for explicit level-shifting and chopping circuits thus facilitating sensing of input signal with zero common-mode. Both PGA and ΔΣ-ADC operate at 2 MHz sampling rate. The signal bandwidth (BW) for the design is 1 KHz with an Over Sampling Ratio(OSR) of 1024. The ΔΣ-ADC when tested stand-alone achieves an SNDR of 84 dB over a signal band of 1 kHz while consuming 2.14 mW of power thus achieving a Schreir's FoM of 163 dB. The complete signal-chain that includes the SC-PGA and ΔΣ-ADC achieves an SNDR of 73 dB while consuming 4.78 mW of power thus realizing a low-power and very sensitive low-side current sensing circuit that can sense currents from 1500 A down to 1 A across a 100 μΩ shunt resistor resulting in a voltage sensitivity of 100 μV and step-size of 36 μV.