A new generation of interconnect technology for high performance electronics

Vishay Siliconix's TrenchFET/sup R/ power MOSFET technology is the result of scaling MOS device dimensions and improving fabrication processes. To fully utilize this new technology in applications involving computer and mobile communication electronics, TrenchFETs must be encapsulated in a compatible miniaturized surface mount package. Consequently, Vishay Siliconix has developed the industry's first surface mount devices with sub-m/spl Omega/ package resistance. This paper presents major performance aspects of modern power MOSFET technology with emphasis on the 32 million-cell trench technology. In addition, we highlight the development methodology and characteristics of new packages that have been used to attain maximum performance. In the course of developing advanced power MOS packages, a 3D finite element study revealed that connecting the MOSFET chip with a limited number of source wire bonds could not guarantee uniformity of current density or voltage distribution across the die's top metal. Emphasis was directed toward optimization of the contact area between package and device surface metallization. Results show that a newly developed 8-lead SOIC package has superior electro-thermal performance when compared with its standard counterparts. A new bonding scheme and a Ni-based metallization process has been developed which enables the device electrical resistance to be reduced by 50%. Also, the new package has over a twofold improvement in power dissipation capability compared to its standard counterparts. This enhancement in performance has been achieved with no increase in manufacturing cost or change in package outline.