A fractional-NBB-DPLL with auto-tuned DTC and FIR filter for noise and spur reduction

A 16-modulo fractional-N bang-bang digital PLL (BB-DPLL) is implemented in 65nm CMOS. It is firstly shown that a hybrid FIR filtering method not only improves spur performance but also reduces in-band phase noise for finite-modulo fractional-N bang-bang PLLs. A 4-bit digital-to-time converter (DTC) with auto-tuned delay cells is also employed to further enhance the fractional-N BB-DPLL performance. Experimental results show that the proposed method reduces both the in-band phase noise and the fractional spur by about 15dB with 4-bit linearity requirement.