Hybrid data/configuration caching for striped FPGAs

Most custom computing machine (CCM) design has centered around field-programmable gate array (FPGA) technology and rapid prototyping applications. FPGAs are reconfigured to map parts of the application. The performance of an FPGA when used as a virtual hardware engine depends on its reconfiguration granularity. We study the striped FPGA and propose a hybrid mechanism to process a large amount of data using a combination of data and configuration caching.